Variable-length decoder (disassembler) is under construction!
Published on March 20, 2022 by Min-Yih Hsu
Sheng (Phab handle: 0x59616e) has been crafting a new (TableGen) infrastructure to emit disassembler code from the new variable-length instruction encoding definitions. This is a crucial infrastructure to generate disassembler for M68k more easily.
Generating disassembler is not an easy task, though. His current approach is augmenting the fixed-length instruction decoder generator since many code can be reused. More specifically, every variable-length instructions are set to be the maximum size in the ISA (for M68k it's 22 bytes), then go through the normal fixed-length decoder generation process -- with some details being different, like operand handling -- before "trimming" the instruction to its real size.
Here are the Phab review entires:
I will keep you updated on the progress.